This invention relates generally to integrated circuit design and construction methods and apparatus and, more particularly, relates to methods and apparatus for embedding computer-readable design-related version information into an integrated circuit.
A problem has arisen as Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) have grown in size and complexity. Specifically, conventional practice stores or embeds within the integrated circuit, such as within a trace register, certain design level or version information that pertains to the entire integrated circuit (e.g., Design Level XYZ). This design level or version information can be subsequently read out of the integrated circuit during system test and/or initialization procedures and can be used for, by example, selecting a particular software driver to work with the specific version of the integrated circuit that is present. In other cases integrated circuit test methodologies may be varied (e.g., timing, maximum test frequencies, etc.) based on the indicated version of the integrated circuit under test.
However, newer integrated circuit synthesis and layout programs allow designers to partition or parse their designs on a single chip or module into multiple partitions and then subsequently load them separately. The conventional practice of providing one design level or version per integrated circuit is thus not adequate for tracking the use of such multiple partitions, and inefficiencies can result. As but one example, a design for a particular complex FPGA may contain a plurality of functional units, each of which requires configuration by serial code that is read out from a memory device during system initialization. As may be appreciated, if a particular version of the FPGA is identical to another version except for an enhancement made to one of the functional units, then it would be advantageous to be able to be made aware of which functional unit differs so that the configuration can be efficiently performed.
It is a first object and advantage of this invention to provide an improved integrated circuit that stores and outputs system-readable information for separately identifying individual ones of a plurality of integrated circuit functional units.
It is another object and advantage of this invention to provide a programmable integrated circuit having a plurality of functional units, wherein during a trace register readout procedure there is output information that is descriptive of individual ones of the function units, such as a version number for each functional unit, as well as ancillary functional unit information and other information, such as a version number for the integrated circuit as a whole.
The foregoing and other problems are overcome and the foregoing objects and advantages are realized by methods and apparatus in accordance with embodiments of this invention.
An integrated circuit device or chip enables a system interface to read multiple design level/version numbers of multiple and independent version numbers per chip to identify independently modifiable sub-sections of the chip (or module) design. The design enables one to store both creation and modification dates and/or version numbers for each sub-section or partition of the chip design, referred to herein generally as functional units. The values can be hard-coded into the design, such as in the case of an ASIC, or they can be placed in a FPGA download design and stored as part of the FPGA configuration procedure. The values can also be stored from the input pins of the integrated circuit. The readout of the version information can be performed via a hardware trace register readout through a system interface. In this manner one is enabled to implement multiple level control to separate the functional and diagnostic area of the chip.